The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the electronics industry utilized various methods and structures to produce power devices that had a low drain to source resistance (Rds(on)). The low Rds(on) reduced the power loss in the power device when the device was on, thus increasing the system efficiency. Typically the devices had high gate capacitances that resulted in a high total gate charge (Qg) and reduced the maximum operating frequency of the devices.
In some applications such as switching power supplies, good switching performance was also required for the power MOSFET, in addition to the low Rds(on). One requirement for such a power MOSFET was a low gate charge (Qg). The gate charge Qg was defined as the charge that had to be supplied to the gate by the driver IC, in order to charge the gate to its operating voltage. For power MOSFETs that were used in the low side of a switching power supply (for example, a buck converter), an additional requirement was good dV/dt performance (i.e. the capability to withstand a high rate of change of drain voltage, without experiencing a false turn-on). In a buck converter, when the high side MOSFET turned on, the switch node (to which the drain of the low side MOSFET was connected), experienced a high dV/dt. This high rate of change of drain voltage in the low side MOSFET caused a spike in the gate voltage. If the magnitude of the gate voltage spike was higher than the threshold voltage (Vth) of the low side MOSFET, then the low side MOSFET turned on. This was called false turn-on and it caused shoot-through current that lowered the efficiency of the system by causing additional power loss. In severe cases, the shoot-through current also caused one of the MOSFETs to fail.
Accordingly, it is desirable to have a method of forming a power device that reduces gate capacitances, that reduces the gate charge ratio Qgd/Qgs(th), and that reduces the total gate charge of the power device while not affecting the Rds(on) of the device significantly.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions are generally not straight lines and the corners are not precise angles.